SH7751 Datasheet, PDF (282/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Floating-Point Unit
FTRV XMTRX, FVn (n: 0, 4, 8, 12): Examples of the use of this instruction are given below.
• Matrix (4 × 4) ⋅ vector (4):
This operation is generally used for viewpoint changes, angle changes, or movements called
vector transformations (4-dimensional). Since affine transformation processing for angle +
parallel movement basically requires a 4 × 4 matrix, the FPU supports 4-dimensional
operations.
• Matrix (4 × 4) × matrix (4 × 4):
This operation requires the execution of four FTRV instructions.
Since approximate-value computations are performed to enable high-speed computation, the
inexact exception (I) bit in the FPU exception cause field and FPU exception flag field is always
set to 1 when an FTRV instruction is executed. Therefore, if the corresponding bit is set in the
FPU exception enable field, FPU exception handling will be executed. For the same reason, it is
not possible to check all data types in the registers beforehand when executing an FTRV
instruction. If the V bit is set in the FPU exception enable field, FPU exception handling will be
executed.
FRCHG: This instruction modifies banked registers. For example, when the FTRV instruction is
executed, matrix elements must be set in an array in the background bank. However, to create the
actual elements of a translation matrix, it is easier to use registers in the foreground bank. When
the LDC instruction is used on FPSCR, this instruction expends 4 to 5 cycles in order to maintain
the FPU state. With the FRCHG instruction, an FPSCR.FR bit modification can be performed in
one cycle.
6.6.2 Pair Single-Precision Data Transfer
The powerful geometric operation instructions, FPU also supports high-speed data transfer
instructions.
When FPSCR.SZ = 1, FPU can perform data transfer by means of pair single-precision data
transfer instructions.
• FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14)
• FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15)
These instructions enable two single-precision (2 × 32-bit) data items to be transferred; that is, the
transfer performance of these instructions is doubled.
Rev.4.00 Oct. 10, 2008 Page 184 of 1122
REJ09B0370-0400