SH7751 Datasheet, PDF (878/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Interrupt Controller (INTC)
19.3 Register Descriptions
19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD)
Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for on-chip peripheral module interrupts. IPRA to IPRC are initialized
to H'0000 and IPRD is to H'DA74 by a reset. They are not initialized in standby mode.
IPRA to IPRC
Bit: 15
14
13
12
11
10
9
8
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IPRD
Bit: 15
14
13
12
11
10
9
8
Initial value:
1
1
0
1
1
0
1
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
1
1
1
0
1
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 19.5 shows the relationship between the interrupt request sources and the IPRA–IPRD
register bits.
Rev.4.00 Oct. 10, 2008 Page 780 of 1122
REJ09B0370-0400