SH7751 Datasheet, PDF (1045/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.3.11 PCI Bus Basic Interface
The PCI interface of the MCU supports a subset of version 2.1 of the PCI specifications and
enables connection to a device with a PCI bus interface.
While the PCIC is set in host mode, or while set in non-host mode, operation differs according to
whether or not bus parking is performed, and whether or not the PCI bus arbiter function is
enabled or not.
In host mode, the AD, PAR, C/BE signal lines are driven by the PCIC when transfers are not
being performed on the PCI bus (bus parking). When the PCIC subsequently starts transfers as
master, these signal lines continue to be driven until the end of the address phase. However, in
non-host mode, the master performing parking is determined according to the GNT output by the
external arbiter. When the master performing parking is not the same master as that starting the
subsequent transfer, a high impedance state of at least one clock is generated prior to the address
phase.
In host mode, the arbiters in the PCICs and the REQ and GNT between PCICs are connected
internally. Here, pins PCIREQ1/GNTIN, PCIREQ2/MD9, PCIREQ3/MD10, and PCIREQ4
function as the REQ inputs from the external masters 1 to 4. Similarly, PCIGNT1/REQOUT,
PCIGNT2, PCIGNT3, and PCIGNT4 function as the GNT outputs to external masters 1 to 4.
Including the PCIC, arbitration of up to five masters is possible.
In non-host mode, pins PCIREQ1/GNTIN functions as the GNT input of the PCIC, while
PCIGNT1/REQOUT functions as the REQ output of the PCIC.
Master Read/Write Cycle Timing: Figures 22.7 is an example of a single-write cycle in host
mode. Figure 22.8 is an example of a single read cycle in host mode. Figure 22.9 is an example of
a burst write cycle in non-host mode. And Figure 22.10 is an example of a burst read cycle in non-
host mode. Note that the response speed of DEVSEL and TRDY differs according to the
connected target device.
In PIO transfers, always use single read/write cycles.
The issuing of configuration transfers is only possible in host mode.
LOCK transfers are possible only using PIO transfers.
Rev.4.00 Oct. 10, 2008 Page 947 of 1122
REJ09B0370-0400