SH7751 Datasheet, PDF (631/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
5. When the transfer request is an external request, only channels 0 and 1 can be used.
6. In DDT mode, transfer requests can be accepted for all channels from external devices
capable of DTR format output.
7. See tables 14.8 and 14.9 for the transfer sources and transfer destinations in DMA
transfer by means of an external request.
(a) Normal DMA Mode
Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer
destination in DMA transfer initiated by an external request supported by this LSI in normal DMA
mode.
Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode
Transfer Direction (Settable Memory Interface)
Transfer Source
Transfer Destination
Usable
Address DMAC
Mode Channels
1 Synchronous DRAM
External device with DACK
Single 0, 1
2 External device with DACK
Synchronous DRAM
Single 0, 1
3 SRAM-type, DRAM
External device with DACK
Single 0, 1
4 External device with DACK
SRAM-type, DRAM
Single 0, 1
5 Synchronous DRAM
SRAM-type, MPX, PCMCIA * Dual
0, 1
6 SRAM-type, MPX, PCMCIA * Synchronous DRAM
Dual
0, 1
7 SRAM-type, DRAM, PCMCIA,
SRAM-type, MPX, PCMCIA * Dual
0, 1
MPX
8 SRAM-type, MPX, PCMCIA * SRAM-type, DRAM, PCMCIA,
Dual
0, 1
MPX
Notes: "SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting.
Memory interfaces on which transfer is possible in single address mode are SRAM, byte
control SRAM, burst ROM, DRAM, and synchronous DRAM.
When performing dual address mode transfer, make the DACK output setting for the
SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
* DACK output setting in dual address mode transfer
Rev.4.00 Oct. 10, 2008 Page 533 of 1122
REJ09B0370-0400