SH7751 Datasheet, PDF (1018/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
Bits 31 to 2—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Bit 1—Power State D3 (DPERR_WT): Transition request to power-down mode interrupt mask
for this LSI.
Bit 0—Power State D0 (DPERR_RD): Restore from power-down mode interrupt mask for this
LSI.
22.2.37 PCI Clock Control Register (PCICLKR)
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value:
0
0
0
...
0
0
0
0
PCI-R/W: —
—
—
...
—
—
—
—
PP Bus-R/W: R
R
R
...
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
— PCICLKS BCLKST
TOP
OP
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R
R/W
R/W
The PCI clock control register (PCICLKR) controls the stopping of the local bus clock (BCLK) in
the PCIC and the PCI bus clock. This 32-bit read/write register can be accessed from the PP bus.
The PCICLKR register is initialized to H'00000000 at a power-on reset. It is not initialized at a
software reset.
When the PCI bus clock is input from the external input pin PCICLK, the PCI bus clock can be
stopped by setting the PCICLKSTOP bit to 1. Likewise, the local bus clock can be stopped by
setting the BCLKSTOP bit to 1.
When the PCI bus clock is input via the CKIO pin, setting BCLKSTOP to 1 stops both the Bck in
the PCIC and the feedback input clock from CKIO.
Writing to this register is valid only when bits 31 to 24 are H'A5.
Rev.4.00 Oct. 10, 2008 Page 920 of 1122
REJ09B0370-0400