SH7751 Datasheet, PDF (867/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Interrupt Controller (INTC)
Section 19 Interrupt Controller (INTC)
19.1 Overview
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to handle interrupt requests according to user-set priority.
19.1.1 Features
The INTC has the following features.
• Fifteen interrupt priority levels can be set
By setting the five interrupt priority registers, the priorities of on-chip peripheral module
interrupts can be selected from 15 levels for different request sources.
• NMI noise canceler function
The NMI input level bit indicates the NMI pin state. The pin state can be checked by reading
this bit in the interrupt exception handler, enabling it to be used as a noise canceler.
• NMI request masking when SR.BL bit is set
It is possible to select whether or not NMI requests are to be masked when the SR.BL bit is set.
19.1.2 Block Diagram
Figure 19.1 shows a block diagram of the INTC.
Rev.4.00 Oct. 10, 2008 Page 769 of 1122
REJ09B0370-0400