SH7751 Datasheet, PDF (1043/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
• Termination by software reset
When the RSTCTL bit of the PCICR is asserted, the PCIC is reset and DMA transfers are
forcibly terminated. Note, however, that when transfers are terminated by a software reset, the
PCIDCR is also reset and the DMA transfer control registers are all cleared.
DMA Arbitration: If transfer requests are made simultaneously on multiple DMA channels in the
PCI, transfer arbitration is required. There are two modes that can be selected to determine order
of priority of the DMA transfers on the four channels: fixed order of priority and pseudo round-
robin. The mode is selected using the DMABT bit of the PCI's DMA transfer arbitration register
(PCIDMABT).
For arbitration to be performed in such a way as to maintain high-speed data transfer, there are 4
FIFOs (32-byte × 2 buffer structure) for the four DMA transfer channels. The FIFOs have a 2-
buffer structure, enabling one buffer to be accessed from the PCI bus while the other is being
accessed from the local bus. Depending on the direction of the transfer, the input port of the FIFO
for DMA transfers. Transfers are possible in both directions between the local bus and PCI bus by
selecting the transfer direction.
The arbitration circuit monitors the data transfer requests (data write requests to the FIFO when
the FIFO is empty and read requests from the FIFO when it is full) 4 DMA transfer channels to
control the data transfers. For each transfer request, a transfer of up to 32 bytes of data is
performed.
If a DMA transfer request occurs at the same time as a PIO transfer request, the PIO transfer takes
precedence over transfers on the four DMA channels, regardless of the specified mode of DMA
transfer priority order.
Fixed Priority Mode (DMABT = 0): In fixed priority mode, the order of priority of data transfer
requests is fixed and cannot be changed. The order is as follows:
Channel 0 DMA transfer > channel 1 DMA transfer > channel 2 DMA transfer >
channel 3 DMA transfer
DMA transfer on channel 0. Take the highest priority and channel 3 DMA transfers take the
lowest priority. When data transfer requests occur simultaneously, the data transfer with the
highest priority takes precedence.
Let's look at data transfers from the local bus to the PCI bus in fixed priority mode. The arbitration
circuit monitors the transfer requests from the respective data transfer control circuits and writes
data read from the local bus to the data transfer FIFO that not only is empty but also has the
highest priority.
Rev.4.00 Oct. 10, 2008 Page 945 of 1122
REJ09B0370-0400