SH7751 Datasheet, PDF (349/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Power-Down Modes
The phase of the CKIO pin clock output may be unstable immediately after an interrupt is
detected, until standby mode is exited.
Notes: 1. Only when the RTC clock (32.768 kHz) is operating (see section 19.2.2, IRL
Interrupts), standby mode can be exited by means of IRL3–IRL0 (when the IRL3–
IRL0 level is higher than the SR register IMASK mask level).
2. GPIC can be used to cancel standby mode when the RTC clock (32.768 kHz) is
operating (when the GPIC level is higher than the SR register IMASK mask level).
Exit by Reset: Standby mode is exited by means of a reset (power-on or manual) via the RESET
pin. The RESET pin should be held low until clock oscillation stabilizes. The internal clock
continues to be output at the CKIO pin.
9.6.3 Clock Pause Function
In standby mode, it is possible to stop or change the frequency of the clock input from the EXTAL
pin. This function is used as follows.
1. Enter standby mode following the transition procedure described above.
2. When standby mode is entered and the chip's internal clock stops, a low-level signal is output
at the STATUS1 pin, and a high-level signal at the STATUS0 pin.
3. The input clock is stopped, or its frequency changed, after the STATUS1 pin goes low and the
STATUS0 pin high.
4. When the frequency is changed, input an NMI or IRL interrupt after the change. When the
clock is stopped, input an NMI or IRL interrupt after applying the clock.
5. After the time set in the WDT, clock supply begins inside the chip, the STATUS1 and
STATUS0 pins both go low, and operation is resumed from interrupt exception handling.
9.7 Module Standby Function
9.7.1 Transition to Module Standby Function
Setting the MSTP6–MSTP0 and CSTP2–CSTP0 bits in the standby control register, standby
control register 2, and clock stop clear register 00 to 1 enables the clock supply to the
corresponding on-chip peripheral modules to be halted. Use of this function allows power
consumption in sleep mode to be further reduced.
In the module standby state, the on-chip peripheral module external pins retain their states prior to
halting of the modules, and most registers retain their states prior to halting of the modules.
Rev.4.00 Oct. 10, 2008 Page 251 of 1122
REJ09B0370-0400