SH7751 Datasheet, PDF (675/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Four requests can be queued
CKIO
1st 2nd 3rd 4th
5th
DBREQ
BAVL
TR
14. Direct Memory Access Controller (DMAC)
Handshaking is necessary
to send additional requests
A25–A0
D31–D0
RAS, CAS,
WE
TDACK
ID1, ID0
RA
CA
CA
CA
CA
D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3
BA
WT
WT
WT
WT
Must be ignored
(no request transmitted)
Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data
Transfer/Direct Data Transfer Request to Channel 2
Rev.4.00 Oct. 10, 2008 Page 577 of 1122
REJ09B0370-0400