SH7751 Datasheet, PDF (802/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Serial Communication Interface with FIFO (SCIF)
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK2 pin can be selected as the SCIF's serial clock, according to the setting of the CKE1 bit in
SCSCR2. For details of SCIF clock source selection, see table 16.4.
When an external clock is input at the SCK2 pin, the clock frequency should be 16 times the bit
rate used.
When operating using the internal clock, the clock can be output via the SCK2 pin. The frequency
of this clock is 16 times the bit rate.
Data Transfer Operations
SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE
bits in SCSCR2 to 0, then initialize the SCIF as described below.
When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making
the change using the following procedure. When the TE bit is cleared to 0, SCTSR2 is initialized.
Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR2, SCFTDR2, or
SCFRDR2. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND
flag in SCFSR2 has been set. TEND can also be cleared to 0 during transmission, but the data
being transmitted will go to the mark state after the clearance. Before setting TE again to start
transmission, the TFRST bit in SCFCR2 should first be set to 1 to reset SCFTDR2.
When an external clock is used the clock should not be stopped during operation, including
initialization, since operation will be unreliable in this case.
Figure 16.7 shows a sample SCIF initialization flowchart.
Rev.4.00 Oct. 10, 2008 Page 704 of 1122
REJ09B0370-0400