SH7751 Datasheet, PDF (222/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
not executed. If a data TLB multiple hit exception occurs during address translation,
processing switches to the data TLB multiple hit exception handling routine.
31
24 23
Address field _{1 1 1 1 0 1 0 0}
14 13
Entry
543210
A
31
10 9
210
Data field
Tag
UV
Legend:
V: Validity bit
U: Dirty bit
A: Association bit
: Reserved bits (0 write value, undefined read value)
Figure 4.10 Memory-Mapped OC Address Array
4.5.4 OC Data Array
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The entry to be accessed is specified in the address field, and the longword
data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the entry is
specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification.
Address field bits [4:2] are used for the longword data specification in the entry. As only longword
access is used, 0 should be specified for address field bits [1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the OC data array:
1. OC data array read
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the OC entry corresponding to the entry set in the address field.
2. OC data array write
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the OC entry corresponding the entry set in the address
field. This write does not set the U bit to 1 on the address array side.
Rev.4.00 Oct. 10, 2008 Page 124 of 1122
REJ09B0370-0400