SH7751 Datasheet, PDF (213/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
Examples
Example 1 A store instruction accessing internal RAM occurs within four instructions after an
instruction generating a TLB miss exception.
MOV.L #H'0C400000, R0
R0 is an address causing a TLB miss.
MOV.L #H'7C000204, R1
R1 is an address mapped to internal RAM.
MOV.L @R0, R2
TLB miss exception occurs.
NOP
1st word
NOP
2nd word
NOP
3rd word
MOV.L R3, @R1
Store instruction accessing internal RAM
Example 2 A store instruction accessing internal RAM occurs within four instructions after an
instruction causing an interrupt to be accepted.
MOV.L #H'7C002000, R1
R1 is an address mapped to internal RAM.
MOV.L #H'12345678, R0
An interrupt is accepted after this instruction.
NOP
1st word
NOP
2nd word
NOP
3rd word
MOV.L R0, @R1
Store instruction accessing internal RAM
Example 3 A debugging tool generates a break to swap an instruction.
Original Instruction String After Instruction Swap Break
MOV.L #H'7C000000, R0 MOV.L #H'7C000000, R0 Contains address corresponding to R0.
ADD R0, R0
TRAPA #H'01
R0 address is not a problem in original
instruction string.
MOV.L R1, @R0
MOV.L R1, @R0
Internal RAM is accessed by a store
operation because ADD is not executed.
The store is cancelled, but 2LW starting
at H'7C002000 is corrupted.
Rev.4.00 Oct. 10, 2008 Page 115 of 1122
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