SH7751 Datasheet, PDF (623/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
1. Transfer requests are issued simultaneously for channels 0 and 3.
2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed
first (channel 3 is on transfer standby).
3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on
transfer standby).
4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level.
5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is
started (channel 3 is on transfer standby).
6. At the end of the channel 1 transfer, channel 1 shifts to the lowest priority level.
7. The channel 3 transfer is started.
8. At the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered,
giving channel 3 the lowest priority.
Transfer request
Channel
1. Issued for channels 0 ^waiting
and 3
3. Issued for channel 1
3
DMAC operation
2. Start of channel 0
transfer
Channel priority
order
0>1>2>3
Change of
priority order
1, 3
4. End of channel 0
transfer
1>2>3>0
5. Start of channel 1
transfer
Change of
priority order
3
6. End of channel 1
2>3>0>1
transfer
None
7. Start of channel 3
transfer
8. End of channel 3
transfer
Change of
priority order
0>1>2>3
Figure 14.4 Example of Changes in Priority Order in Round Robin Mode
Rev.4.00 Oct. 10, 2008 Page 525 of 1122
REJ09B0370-0400