SH7751 Datasheet, PDF (169/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Memory Management Unit (MMU)
3.3 Address Space
3.3.1 Physical Address Space
The SH-4 supports a 32-bit physical address space, and can access a 4-Gbyte address space. When
the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical
address space. The physical address space is divided into a number of areas, as shown in figure
3.3. The physical address space is permanently mapped onto 29-bit external memory space; this
correspondence can be implemented by ignoring the upper 3 bits of the physical address space
addresses. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed.
In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing the P1 to P4 areas
(except the store queue area) in user mode will cause an address error.
H'0000 0000
P0 area
Cacheable
External
memory space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
H'0000 0000
U0 area
Cacheable
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
P1 area
Cacheable
P2 area
Non-cacheable
P3 area
Cacheable
P4 area
Non-cacheable
Privileged mode
H'8000 0000
Address error
Store queue area
Address error
User mode
H'E000 0000
H'E400 0000
H'FFFF FFFF
Figure 3.3 Physical Address Space (MMUCR.AT = 0)
When performing access from the CPU to a PCMCIA interface area in the SH-4, access is always
performed using the values of the SA and TC bits set in the PTEA register. Access to a PCMCIA
interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn,
Rev.4.00 Oct. 10, 2008 Page 71 of 1122
REJ09B0370-0400