SH7751 Datasheet, PDF (569/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
13.3.8 MPX Interface
If the MD6 pin is cleared to 0 in a power-on reset by means of the RESET pin, the MPX interface
is selected for area 0. The MPX interface is selected for areas 1 to 6 by means of the MPX bit in
BCR1 and MEMMODE, A4MPX, and A1MPX in BCR3. The MPX interface offers a multiplexed
address/data type bus protocol, and permits easy connection to an external memory controller chip
that uses a single 32-bit multiplexed address/data bus. A bus cycle consists of an address phase
and a data phase, with address information output to D25–D0 and the access size output to D31–
D29 in the address phase. The BS signal is asserted for one cycle to indicate the address phase.
The CSn signal is asserted at the rise of Tm1 and negated after the end of the last data transfer in
the data phase. Therefore, a negation period does not occur in the case of minimum pitch access.
The FRAME signal is asserted at the rise of Tm1 and negated when the last data transfer cycle
starts in the data phase. Therefore, an external device for the MPX interface must hold the address
information and access size output in the address phase within itself, and peripheral function data
input/output for the data phase. For details of access sizes and data alignment, see section 13.3.1,
Endian/Access Size and Data Alignment.
Values output to address pins A25–A0 are not guaranteed.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed on 32-byte boundary data. If the access size exceeds the set bus width in
this case, burst access is performed with a number of data cycles following one address output.
The bus is not released during this period.
D31
D30
D29
0
0
0
1
1
0
1
1
X
X
Legend: X: Don't care
Access Size
Byte
Word
Longword
Quadword
32-byte burst
Rev.4.00 Oct. 10, 2008 Page 471 of 1122
REJ09B0370-0400