SH7751 Datasheet, PDF (86/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 23.12 (1) Pin Drive Timing for Standby Mode ...........................................................
Figure 23.12 (2) Pin Drive Timing for Software Standby Mode............................................
Figure 23.13 SRAM Bus Cycle: Basic Bus Cycle (No Wait) .................................................
Figure 23.14 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) ..................................
Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)
Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/
Hold Time Insertion, AnS = 1, AnH = 1)...........................................................
Figure 23.17 Burst ROM Bus Cycle (No Wait) ......................................................................
Figure 23.18 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait;
2nd/3rd/4th Data: One Internal Wait).................................................................
Figure 23.19 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion,
AnS = 1, AnH = 1) .............................................................................................
Figure 23.20 Burst ROM Bus Cycle (One Internal Wait + One External Wait) .....................
Figure 23.21 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single
(RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) ......................................
Figure 23.22 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst
(RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) ......................................
Figure 23.23 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands,
Burst (RASD = 1, RCD [1:0] = 01, CAS Latency = 3)......................................
Figure 23.24 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ
Commands, Burst (RASD = 1, RCD [1:0] = 01, TPC [2:0] = 001,
CAS Latency = 3)...............................................................................................
Figure 23.25 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst
(RASD = 1, CAS Latency = 3) ..........................................................................
Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single
(RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)....................................
Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst
(RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)....................................
Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands,
Burst (RASD = 1, RCD [1:0] = 01, TRWL [2:0] = 010) ...................................
Figure 23.29 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT +
WRITE Commands, Burst (RASD = 1, RCD [1:0] = 01, TPC [2:0] = 001,
TRWL [2:0] = 010) ............................................................................................
Figure 23.30 Synchronous DRAM Normal Write Bus Cycle: WRITE Command,
Burst (RASD = 1, TRWL [2:0] = 010) ..............................................................
Figure 23.31 Synchronous DRAM Bus Cycle: Precharge Command (TPC [2:0] = 001) .......
Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001)
Figure 23.33 Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001) ....................
Figure 23.34 (a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL)...............
Figure 23.34 (b) Synchronous DRAM Bus Cycle: Mode Register Setting (SET) .................
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Rev.4.00 Oct. 10, 2008 Page lxxxvi of xcviii
REJ09B0370-0400