SH7751 Datasheet, PDF (961/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.2.3 PCI Configuration Register 2 (PCICONF2)
Bit: 31
30
29
28
27
26
25
24
CLASS23 CLASS22 CLASS21 CLASS20 CLASS19 CLASS18 CLASS17 CLASS16
Initial value: —
—
—
—
—
—
—
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
19
18
17
16
CLASS15 CLASS14 CLASS13 CLASS12 CLASS11 CLASS10 CLASS9 CLASS8
Initial value: —
—
—
—
—
—
—
—
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
8
CLASS7 CLASS6 CLASS5 CLASS4 CLASS3 CLASS2 CLASS1 CLASS0
Initial value: —
—
—
—
—
—
—
—
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
REVID7 REVID6 REVID5 REVID4 REVID3 REVID2 REVID1 REVID0
Initial value:
*
*
*
*
*
*
*
*
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Note: * Initial values vary with the logic versions of the chip.
The PCI configuration register 2 (PCICONF2) is a 32-bit read/partial-write register that includes
the class code and revision ID PCI configuration registers stipulated in the PCI local bus
specifications. Bits 31 to 8 (class code) set the device functions. The chip logic version can be
read from bits 7 to 0 (revision ID).
Bits 31 to 8 can be written to from the PP bus. Bits 7 to 0 are fixed in hardware.
The PCICONF2 register class codes are not initialized at a reset. They must be initialized while
CFINIT (bit 0) of the PCI control registers (PCICR) is cleared.
Rev.4.00 Oct. 10, 2008 Page 863 of 1122
REJ09B0370-0400