SH7751 Datasheet, PDF (34/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page Revision (See Manual for Details)
15.3.3 Multiprocessor
Communication
Function
649, 650 Description amended
Multiprocessor Serial Data Reception
1. Method for determining whether an interrupt generated during
receive operation is a multiprocessor interrupt
When an interrupt such as RXI occurs during receive
operation using the on-chip SCI multiprocessor
communication function, check the state of the MPIE bit in
the SCSCR1 register as part of the interrupt handling routine.
a. If the MPIE bit in the SCSCR1 register is set to 1
Ignore the received data.
Data with the multiprocessor bit (MPB) set to 0 and
intended for another station was received, and the RDRF
bit in the SCSCR1 register was set to 1. Therefore, clear
the RDRF bit in the SCSCR1 register to 0.
b. If the MPIE bit in the SCSCR1 register is cleared to 0
A multiprocessor interrupt indicating that data (ID) with the
multiprocessor bit (MPB) set to 1 was received, or a
receive data full interrupt (RXI) occurred when data with
the multiprocessor bit (MPB) set to 0 and intended for this
station was received.
2. Method for determining whether received data is ID or data
Do not use the MPB bit in the SCSSR1 register for software
processing.
When using software processing to determine whether
received data is ID (MPB = 1) or data (MPB = 0), use a
procedure such as saving a user-defined flag in memory to
indicate receive start.
Figure 15.15 shows a flowchart of a sample software
workaround.
Figure 15.15 Sample 651
Flowchart of
Multiprocessor Serial
Reception with Interrupt
Generation
Newly added
Rev.4.00 Oct. 10, 2008 Page xxxiv of xcviii
REJ09B0370-0400