SH7751 Datasheet, PDF (527/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Address Multiplexing: Synchronous DRAM can be connected without external multiplexing
circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2–
AMX0 in MCR. Table 13.15 shows the relationship between the address multiplex specification
bits and the bits output at the address pins. See Appendix E, Synchronous DRAM Address
Multiplexing Tables.
The address signals output at address pins A25–A18, A1, and A0 are not guaranteed.
When A0, the LSB of the synchronous DRAM address, is connected to this LSI, it makes a
longword address specification. Connection should therefore be made in this order: connect pin
A0 of the synchronous DRAM to pin A2 of this LSI, then connect pin A1 to pin A3.
Table 13.15 Example of Correspondence between LSI and Synchronous DRAM Address
Pins (32-Bit Bus Width, AMX2–AMX0 = 000, AMXEXT = 0)
LSI Address Pin
Synchronous DRAM Address Pin
RAS Cycle CAS Cycle
Function
A13
A21
A21
A11
BANK select bank address
A12
A20
H/L
A10
Address precharge setting
A11
A19
0
A9
Address
A10
A18
0
A8
A9
A17
A9
A7
A8
A16
A8
A6
A7
A15
A7
A5
A6
A14
A6
A4
A5
A13
A5
A3
A4
A12
A4
A2
A3
A11
A3
A1
A2
A10
A2
A0
A1
Not used Not used Not used
A0
Not used Not used Not used
Burst Read: The timing chart for a burst read is shown in figure 13.24. In the following example
it is assumed that two 512k × 16-bit × 2-bank synchronous DRAMs are connected, and a 32-bit
data width is used. The burst length is 4. After the Tr cycle in which the ACTV command is
output, a READ command is issued in the Tc1 cycle and, 4 cycles after that, a READA command
is issued and read data is fetched on the rising edge of the external command clock (CKIO) from
cycle Td1 to cycle Td8. The Tpc cycle is used to wait for completion of auto-precharge based on
Rev.4.00 Oct. 10, 2008 Page 429 of 1122
REJ09B0370-0400