SH7751 Datasheet, PDF (1024/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.2.40 Port Data Register (PCIPDTR)
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value:
0
0
0
...
0
0
0
0
PCI-R/W: —
—
—
...
—
—
—
—
PP Bus-R/W: R
R
R
...
R
R
R
R
Bit:
7
—
Initial value:
0
PCI-R/W: —
PP Bus-R/W: R
6
5
4
3
2
1
0
— PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT
0
0
0
0
0
0
0
—
—
—
—
—
—
—
R
R/W
R/W
R/W
R/W
R/W
R/W
The port data register (PCIPDTR) inputs and outputs the port data when allocation of the port
function to the unwanted PCI bus arbitration pins is enabled when the PCIC is operating in non-
host mode. This 32-bit read/write register can be accessed from the PP bus.
The PCIPDTR register is intialized to H'00000000 at a power-on reset. It is not initialized at a
software reset.
Data is output in sync with the local bus clock. Input data is fetched at the rising edge of the local
bus clock.
Bits 31 to 6—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Bit 5—Port 2 Output Data (PB5DT): Output data when PCIGNT4 pin is used as port.
(PCIGNT4 pin is output-only.)
Bit 4—Port 2 Input/Output Data (PB4DT): Receives input data and sets output data when the
PCIREQ4 pin is used as a port.
Bit 3—Port 1 Output Data (PB3DT): Output data when PCIGNT3 pin is used as port.
(PCIGNT3 pin is output-only.)
Bit 2—Port 1 Input/Output Data (PB2DT): Receives input data and sets output data when the
PCIREQ3 pin is used as a port.
Rev.4.00 Oct. 10, 2008 Page 926 of 1122
REJ09B0370-0400