SH7050 Datasheet, PDF (97/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 6 Interrupt Controller (INTC)
6.1.3 Pin Configuration
Table 6.1 shows the INTC pin configuration.
Table 6.1 Pin Configuration
Name
Abbreviation I/O
Non-maskable interrupt input pin NMI
I
Interrupt request input pins
IRQ0–IRQ7 I
Interrupt request output pin
IRQOUT
O
Function
Input of non-maskable interrupt
request signal
Input of maskable interrupt request
signals
Output of notification signal when an
interrupt has occurred
6.1.4 Register Configuration
The INTC has the 10 registers shown in table 6.2. These registers set the priority of the interrupts
and control external interrupt input signal detection.
Table 6.2 Register Configuration
Name
Abbr. R/W Initial Value Address
Access Sizes
Interrupt priority register A IPRA R/W H'0000
H'FFFF8348 8, 16, 32
Interrupt priority register B IPRB R/W H'0000
H'FFFF834A 8, 16, 32
Interrupt priority register C IPRC R/W H'0000
H'FFFF834C 8, 16, 32
Interrupt priority register D IPRD R/W H'0000
H'FFFF834E 8, 16, 32
Interrupt priority register E IPRE R/W H'0000
H'FFFF8350 8, 16, 32
Interrupt priority register F IPRF R/W H'0000
H'FFFF8352 8, 16, 32
Interrupt priority register G IPRG R/W H'0000
H'FFFF8354 8, 16, 32
Interrupt priority register H
Interrupt control register
IRQ status register
IPRH
ICR
ISR
R/W H'0000
R/W ^*1
R(W)^*2 H'0000
H'FFFF8356
H'FFFF8358
H'FFFF835A
8, 16, 32
8, 16, 32
8, 16, 32
Notes: Two access cycles are required for byte access and word access, and four cycles for
longword access.
1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000.
2. Only 0 can be written, in order to clear flags.
Rev. 5.00 Jan 06, 2006 page 77 of 818
REJ09B0273-0500