SH7050 Datasheet, PDF (249/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
TIOR2A is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bit 7—Reserved: This bit is always read as 0, and should only be written with 0.
Bits 6 to 4—I/O Control 1B2 to 1B0, 1D2 to 1D0, 1F2 to 1F0, 2B2 to 2B0 (IO1B2 to IO1B0,
IO1D2 to IO1D0, IOF12 to IO1F0, IO2B2 to IO2B0): These bits select the general register
(GR) function.
Bit 6:
IOxx2
0
Bit 5:
IOxx1
0
Bit 4:
IOxx0
0
1
1
0
1
1
0
0
1
1
0
1
Description
GR is an output
compare register
GR is input capture
register
0 output regardless of compare-match
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge
Input capture in GR on falling edge
Input capture in GR on both rising and
falling edges
Bit 3—Reserved: This bit is always read as 0, and should only be written with 0.
Bits 2 to 0—I/O Control 1A2 to 1A0, 1C2 to 1C0, 1E2 to 1E0, 2A2 to 2A0 (IO1A2 to IO1A0,
IO1C2 to IO1C0, IO1E2 to IO1E0, IO2A2 to IO2A0): These bits select the general register
(GR) function.
Rev. 5.00 Jan 06, 2006 page 229 of 818
REJ09B0273-0500