SH7050 Datasheet, PDF (324/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.3.16 PWM Output Operation at Start of Channel 6 to 9 Counter
In channels 6 to 9, the maximum TCNT input clock error occurs between the cycle register value
or duty register value and the actual output waveform in the waveform of the first cycle when the
free-running counter starts (there is no error in the waveform in the second and subsequent cycles).
This is because the counter start signal from the CPU cannot be determined in synchronization
with the TCNT input clock timing. To output a waveform with no error in the waveform of the
first cycle, the initial value of the duty register (DTR) should be set to H'0000 (in this case,
however, the interrupt status flag will be set when 1 is first output).
The timing in this case is shown in figure 10.28. In this example, H'0003 is set as the duty register
value, and H'0005 as the cycle register value.
Cycle
TCNT
0001 0002 0003 0004 0005 0001 0002 0003 0004 0005 0001 0002 0003 0004
TCNT input clock
Counter start signal
PWM output
Duty
Interrupt status flag
Error with respect
to counter start
1st cycle
2nd cycle
3rd cycle
Figure 10.28 Channel 6 to 9 PWM Output Waveform
Rev. 5.00 Jan 06, 2006 page 304 of 818
REJ09B0273-0500