SH7050 Datasheet, PDF (274/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 1—Input Capture Interrupt Enable (ICE0B): Enables or disables ICI0B requests when the
input capture flag (ICF0B) in TSR is set to 1.
Bit 1:
ICE0B
0
1
Description
ICI0B interrupt requested by ICF0B is disabled
ICI0B interrupt requested by ICF0B is enabled
(Initial value)
Bit 0—Input Capture Interrupt Enable (ICE0A): Enables or disables ICI0A requests when the
input capture flag (ICF0A) in TSR is set to 1.
Bit 0:
ICE0A
0
1
Description
ICI0A interrupt requested by ICF0A is disabled
ICI0A interrupt requested by ICF0A is enabled
(Initial value)
Timer Interrupt Enable Register B (TIERB)
TIERB controls enabling/disabling of channel 1 input capture, compare-match, and overflow
interrupt requests.
Bit: 7
—
Initial value: 0
R/W: R
6
OVE1
0
R/W
5
IME1F
0
R/W
4
IME1E
0
R/W
3
IME1D
0
R/W
2
IME1C
0
R/W
1
IME1B
0
R/W
0
IME1A
0
R/W
Bit 7—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 6—Overflow Interrupt Enable (OVE1): Enables or disables interrupt requests by OVF1 in
TSR when OVF1 is set to 1.
Bit 6:
OVE1
0
1
Description
OVI1 interrupt requested by OVF1 is disabled
OVI1 interrupt requested by OVF1 is enabled
(Initial value)
Rev. 5.00 Jan 06, 2006 page 254 of 818
REJ09B0273-0500