SH7050 Datasheet, PDF (740/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Timer Status Register AL (TSRAL)
H'FFFF8285 (Channel 0) 8
ATU
Bit: 7
6
5
4
Bit name: —
—
—
OVF0
Initial value: 0
0
0
0
R/W: R
R
R R/(W)*
Note: * Only 0 can be written to clear the flag.
3
ICF0D
0
R/(W)*
2
ICF0C
0
R/(W)*
1
ICF0B
0
R/(W)*
0
ICF0A
0
R/(W)*
Bit
Bit Name
Value Description
4
Overflow flag
(OVF0)
0
[Clearing condition]
(Initial value)
Read OVF0 when OVF0 =1, then write 0 in OVF0
1
[Setting condition]
TCNT0 overflowed from H'FFFFFFFF to H'00000000
3
Input capture flag 0
[Clearing condition]
(Initial value)
(ICF0D)
Read ICF0D when ICF0D =1, then write 0 in ICF0D
1
[Setting condition]
TCNT0 value is transferred to input capture register
ICR0D by an input capture signal
2
Input capture flag 0
[Clearing condition]
(Initial value)
(ICF0C)
Read ICF0C when ICF0C =1, then write 0 in ICF0C
1
[Setting condition]
TCNT0 value is transferred to input capture register
ICR0C by an input capture signal
1
Input capture flag 0
[Clearing conditions]
(Initial value)
(ICF0B)
1. Read ICF0B when ICF0B =1, then write 0 in ICF0B
2. When cleared by the DMAC in data transfer
1
[Setting condition]
TCNT0 value is transferred to input capture register
ICR0B by an input capture signal
0
Input capture flag 0
[Clearing condition]
(Initial value)
(ICF0A)
Read ICF0A when ICF0A =1, then write 0 in ICF0A
1
[Setting condition]
TCNT0 value is transferred to input capture register
ICR0A by an input capture signal
Rev. 5.00 Jan 06, 2006 page 720 of 818
REJ09B0273-0500