SH7050 Datasheet, PDF (376/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 12 Watchdog Timer (WDT)
12.1.2 Block Diagram
Figure 12.1 is the block diagram of the WDT.
ITI
(interrupt
signal)
WDTOVF
Internal
reset signal*
Interrupt
control
Overflow
Reset
control
Clock
Clock
select
φ/2
φ/64
φ/128
φ/256
φ/512
φ/1024
φ/4096
φ/8192
Internal
clock sources
RSTCSR
TCNT
TCSR
Module bus
Bus
interface
WDT
TCSR: Timer control/status register
TCNT: Timer counter
RSTCSR: Reset control/status register
Note: The internal reset signal can be generated by setting the register.
The type of reset can be selected (power-on or manual).
Figure 12.1 WDT Block Diagram
12.1.3 Pin Configuration
Table 12.1 shows the pin configuration.
Table 12.1 Pin Configuration
Pin
Abbreviation I/O
Watchdog timer overflow WDTOVF
O
Function
Outputs the counter overflow signal in the
watchdog timer mode
Rev. 5.00 Jan 06, 2006 page 356 of 818
REJ09B0273-0500