SH7050 Datasheet, PDF (285/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 7—A/D Converter Interval Activation Bit 3 (ITVAD3): A/D converter activation setting bit
corresponding to bit 13 in free running counter 0L (TCNT0L). The rise of bit 13 in TCNT0L is
ANDed with ITVAD3, and the result is output to the A/D converter as an activation signal.
Bit 7:
ITVAD3
0
1
Description
A/D converter activation by ATU is disabled
A/D converter activation by ATU is enabled
(Initial value)
Bit 6—A/D Converter Interval Activation Bit 2 (ITVAD2): A/D converter activation setting bit
corresponding to bit 12 in TCNT0L. The rise of bit 12 in TCNT0L is ANDed with ITVAD2, and
the result is output to the A/D converter as an activation signal.
Bit 6:
ITVAD2
0
1
Description
A/D converter activation by ATU is disabled
A/D converter activation by ATU is enabled
(Initial value)
Bit 5—A/D Converter Interval Activation Bit 1 (ITVAD1): A/D converter activation setting bit
corresponding to bit 11 in TCNT0L. The rise of bit 11 in TCNT0L is ANDed with ITVAD1, and
the result is output to the A/D converter as an activation signal.
Bit 5:
ITVAD1
0
1
Description
A/D converter activation by ATU is disabled
A/D converter activation by ATU is enabled
(Initial value)
Bit 4—A/D Converter Interval Activation Bit 0 (ITVAD0): A/D converter activation setting bit
corresponding to bit 10 in TCNT0L. The rise of bit 10 in TCNT0L is ANDed with ITVAD0, and
the result is output to the A/D converter as an activation signal.
Bit 4:
ITVAD0
0
1
Description
A/D converter activation by ATU is disabled
A/D converter activation by ATU is enabled
(Initial value)
Rev. 5.00 Jan 06, 2006 page 265 of 818
REJ09B0273-0500