SH7050 Datasheet, PDF (119/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 7 User Break Controller (UBC)
UBAMRL:
Bit: 15
14
13
12
11
10
UBAMRL UBM15 UBM14 UBM13 UBM12 UBM11 UBM10
Initial value: 0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W
9
UBM9
0
R/W
8
UBM8
0
R/W
Bit:
UBAMRL
Initial value:
R/W:
7
UBM7
0
R/W
6
UBM6
0
R/W
5
UBM5
0
R/W
4
UBM4
0
R/W
3
UBM3
0
R/W
2
UBM2
0
R/W
1
UBM1
0
R/W
0
UBM0
0
R/W
The user break address mask register (UBAMR) consists of user break address mask register H
(UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit
readable/writable registers. UBAMRH designates whether to mask any of the break address bits
established in the UBARH, and UBAMRL designates whether to mask any of the break address
bits established in the UBARL. UBAMRH and UBAMRL are initialized by a power on reset to
H'0000. They are not initialized in software standby mode.
UBAMRH Bits 15 to 0—User Break Address Mask 31 to 16 (UBM31 to UBM16): These bits
designate whether to mask any of the break address 31 to 16 bits (UBA31 to UBA16) established
in the UBARH.
UBAMRL Bits 15 to 0—User Break Address Mask 15 to 0 (UBM15 to UBM0): These bits
designate whether to mask any of the break address 15 to 0 bits (UBA15 to UBA0) established in
the UBARL.
Bits 15–0: UBMn
0
1
Note: n = 31 to 0
Description
Break address UBAn is included in the break conditions (initial value)
Break address UBAn is not included in the break conditions
Rev. 5.00 Jan 06, 2006 page 99 of 818
REJ09B0273-0500