SH7050 Datasheet, PDF (181/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Direct Address Transfer Mode: Data is read from the transfer source during the data read cycle,
and written to the transfer destination during the write cycle, so transfer is conducted in two bus
cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external
memory transfer shown in figure 9.7, data is read from one of the memories by the DMAC during
a read cycle, then written to the other external memory during the subsequent write cycle. Figure
9.8 shows the timing for this operation.
1st bus cycle
DMAC
SAR
Memory
DAR
Transfer source
module
Data buffer
Transfer destination
module
1st bus cycle
The SAR value is taken as the address, and data is read from the transfer source
module and stored temporarily in the DMAC.
2nd bus cycle
DMAC
SAR
DAR
Data buffer
Memory
Transfer source
module
Transfer destination
module
2nd bus cycle
The DAR value is taken as the address, and data stored in the DMAC's data
buffer is written to the transfer destination module.
Figure 9.7 Direct Address Operation during Dual Address Mode
Rev. 5.00 Jan 06, 2006 page 161 of 818
REJ09B0273-0500