SH7050 Datasheet, PDF (209/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
9.3.13 DMAC Access from CPU
The space addressed by the DMAC is 3-cycle space. Therefore, when the CPU becomes the bus
master and accesses the DMAC, a minimum of three basic clock (CLK) cycles are required for
one bus cycle. Also, since the DMAC is located in word space, while a word-size access to the
DMAC is completed in one bus cycle, a longword-size access is automatically divided into two
word accesses, requiring two bus cycles (six basic clock cycles). These two bus cycles are
executed consecutively; a different bus cycle is never inserted between the two word accesses.
This applies to both write accesses and read accesses.
9.4 Examples of Use
9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory
In this example, on-chip serial communication interface channel 0 (SCI0) received data is
transferred to external memory using the DMAC channel 3.
Table 9.7 indicates the transfer conditions and the setting values of each of the registers.
Table 9.7 Transfer Conditions and Register Set Values for Transfer between On-chip SCI
and External Memory
Transfer Conditions
Transfer source: RDR0 of on-chip SCI0
Transfer destination: external memory
Transfer count: 64 times
Transfer source address: fixed
Transfer destination address: incremented
Transfer request source: SCI0 (RDR0)
Bus mode: cycle steal
Transfer unit: byte
Interrupt request generation at end of transfer
Channel priority ranking: 0 > 1 > 2 > 3
Register
SAR0
DAR0
DMATCR0
CHCR0
DMAOR
Value
H'FFFF81A5
H'00400000
H'00000040
H'00004905
H'0001
Rev. 5.00 Jan 06, 2006 page 189 of 818
REJ09B0273-0500