SH7050 Datasheet, PDF (161/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
…
…
Initial value: —
—
—
…
R/W: R/W R/W R/W
…
…
2
1
0
…
…
—
—
—
…
R/W R/W R/W
9.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify
the destination address of a DMA transfer. These registers have a count function, and during a
DMA transfer, they indicate the next destination address. In single-address mode, DAR values are
ignored when a device with DACK has been specified as the transfer destination.
Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when
performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set.
The value after power-on resets and in standby mode is undefined.
Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
…
…
Initial value: —
—
—
…
R/W: R/W R/W R/W
…
…
2
1
0
…
…
—
—
—
…
R/W R/W R/W
Rev. 5.00 Jan 06, 2006 page 141 of 818
REJ09B0273-0500