SH7050 Datasheet, PDF (287/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.2.10 Down-Count Start Register (DSTR)
The down-count start register (DSTR) is an 8-bit register. The ATU has one DSTR register in
channel 10.
Bit: 7
6
5
4
3
2
1
0
DST10H DST10G DST10F DST10E DST10D DST10C DST10B DST10A
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only 1 can be written.
DSTR is an 8-bit readable/writable register that starts and stops the channel 10 down-counter
(DCNT).
When the one-shot pulse function is used, a value of 1 can be set in a DST10 bit at any time by the
user program. The DST10 bits are cleared to 0 automatically when the DCNT value underflows.
When the offset one-shot pulse function is used, a DST10 bit is automatically set to 1 when a
compare-match occurs between the channel 1 or 2 free-running counter (TCNT) and a general
register (GR) while the corresponding timer connection register (TCNR) bit is set to 1. The bit is
automatically cleared to 0 when the DCNT value underflows. A value of 1 can be set in a DST10
bit at any time by the user program.
DSTR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
For details, see sections 10.3.5, One-Shot Pulse Function, and 10.3.6, Offset One-Shot Pulse
Function.
Rev. 5.00 Jan 06, 2006 page 267 of 818
REJ09B0273-0500