SH7050 Datasheet, PDF (486/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 15 Compare Match Timer (CMT)
CMCNT value
CMCOR
Counter cleared by
CMCOR compare match
H'0000
Figure 15.2 Counter Operation
Time
15.3.2 CMCNT Count Timing
One of four clocks (φ/8, φ/32, φ/128, φ/512) obtained by dividing the system clock (CK) can be
selected by the CKS1, CKS0 bits of the CMCSR. Figure 15.3 shows the timing.
CK
Internal clock
CMCNT input
clock
CMCNT
N–1
N
Figure 15.3 Count Timing
N+1
15.4 Interrupts
15.4.1 Interrupt Sources and DTC Activation
The CMT has a compare match interrupt for each channel, with independent vector addresses
allocated to each of them. The corresponding interrupt request is output when the interrupt request
flag CMF is set to 1 and the interrupt enable bit CMIE has also been set to 1.
When activating CPU interrupts by interrupt request, the priority between the channels can be
changed by using the interrupt controller settings. See section 6, Interrupt Controller, for details.
Rev. 5.00 Jan 06, 2006 page 466 of 818
REJ09B0273-0500