SH7050 Datasheet, PDF (524/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 16 Pin Function Controller (PFC)
16.3.11 Port F IO Register (PFIOR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
—
—
—
—
PF11 PF10 PF9
IOR IOR IOR
PF8
IOR
PF7
IOR
PF6
IOR
PF5
IOR
PF4
IOR
PF3
IOR
PF2
IOR
PF1
IOR
PF0
IOR
Initial value: 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The port F IO register (PFIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 12 pins in port F. Bits PF11IOR to PF0IOR correspond to pins
PF11/BREQ/PULS7 to PF0/IRQ0. PFIOR is enabled when port F pins function as general
input/output pins (PF11 to PF0) or the PF8/SCK2/PULS4 pin has the serial clock function
(SCK2), and is disabled otherwise.
When port F pins function as PF11 to PF0 or include the SCK2 function, a pin becomes an output
when the corresponding bit in PFIOR is set to 1, and an input when the bit is cleared to 0.
PFIOR is initialized to H'F000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
16.3.12 Port F Control Registers 1 and 2 (PFCR1, PFCR2)
Port F control registers 1 and 2 (PFCR1, PFCR2) are 16-bit readable/writable registers that select
the functions of the 12 multiplex pins in port F. PFCR1 selects the functions of the pins for the
upper 4 bits in port F, and PFCR2 selects the functions of the pins for the lower 8 bits in port F.
PFCR1 and PFCR2 are initialized to H'FF00 and H'00AA, respectively, by a power-on reset
(excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in
software standby mode or sleep mode.
Rev. 5.00 Jan 06, 2006 page 504 of 818
REJ09B0273-0500