SH7050 Datasheet, PDF (397/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 13 Serial Communication Interface (SCI)
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source of the on-chip baud rate generator. Four clock sources are available; φ, φ/4, φ/16, or φ/64.
For further information on the clock source, bit rate register settings, and baud rate, see section
13.2.8, Bit Rate Register.
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
φ (initial value)
φ/4
φ/16
φ/64
13.2.6 Serial Control Register (SCR)
The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock
output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCR. The SCR is initialized
to H'00 by a power-on reset, in hardware standby mode and software standby mode. Manual reset
does not initialize SCR.
Bit: 7
6
5
4
3
2
1
0
TIE
RIE
TE
RE MPIE TEIE CKE1 CKE0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TxI) requested when the transmit data register empty bit (TDRE) in the serial status register
(SSR) is set to 1 by transfer of serial transmit data from the TDR to the TSR.
Bit 7: TIE
0
1
Description
Transmit-data-empty interrupt request (TxI) is disabled (initial value).
The TxI interrupt request can be cleared by reading TDRE after it has
been set to 1, then clearing TDRE to 0, or by clearing TIE to 0.
Transmit-data-empty interrupt request (TxI) is enabled
Rev. 5.00 Jan 06, 2006 page 377 of 818
REJ09B0273-0500