SH7050 Datasheet, PDF (225/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Block Diagram of Channel 5: Figure 10.6 shows a block diagram of ATU channel 5.
TSTR
TCLKA
TCLKB
φ/(m·2ⁿ)
1 ≤ m ≤ 32
0≤n≤5
Clock selection
Comparator
Control logic
OVI5
IMI5A
IMI5B
TIOA5
TIOB5
Module data bus
Legend:
TSTR: Timer start register (16 bits)
TMDR: Timer mode register (8 bits)
TCR5: Timer control register 5 (8 bits)
TIOR5A: Timer I/O control register 5A (8 bits)
TSRDL: Timer status register DL (8 bits)
TIERDL: Timer interrupt enable register DL (8 bits)
TCNT5: Free-running counter 5 (16 bits)
GR5: General register 5 (16 bits)
Interrupts:
OVI5: Overflow interrupt 5
IMI5: Input capture/compare-match interrupt 5
Note: * TMDR is used by channels 3 to 5.
TSRDH and TIERDH are used by channels 4 and 5.
Figure 10.6 Block Diagram of Channel 5
Rev. 5.00 Jan 06, 2006 page 205 of 818
REJ09B0273-0500