SH7050 Datasheet, PDF (256/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Timer Status Registers AH and AL (TSRAH, TSRAL)
TSRAH indicates the status of channel 0 interval interrupts.
Bit: 7
6
5
4
—
—
—
—
Initial value: 0
0
0
0
R/W: R
R
R
R
Note: * Only 0 can be written, to clear the flag.
3
IIF3
0
R/(W)*
2
IIF2
0
R/(W)*
1
IIF1
0
R/(W)*
0
IIF0
0
R/(W)*
Bits 7 to 4—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 3—Interval Interrupt Flag (IIF3): Status flag that indicates the generation of an interval
interrupt.
Bit 3:
IIF3
0
1
Description
[Clearing condition]
When IIF3 is read while set to 1, then 0 is written in IIF3
[Setting condition]
When 1 is generated by AND of ITVE3 in ITVRR and bit 13 of TCNT0L
(Initial value)
Bit 2—Interval Interrupt Flag (IIF2): Status flag that indicates the generation of an interval
interrupt.
Bit 2:
IIF2
0
1
Description
[Clearing condition]
When IIF2 is read while set to 1, then 0 is written in IIF2
[Setting condition]
When 1 is generated by AND of ITVE2 in ITVRR and bit 12 of TCNT0L
(Initial value)
Rev. 5.00 Jan 06, 2006 page 236 of 818
REJ09B0273-0500