SH7050 Datasheet, PDF (46/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 2 CPU
Delayed Branch Instructions: Unconditional branch instructions are delayed. Executing the
instruction that follows the branch instruction and then branching reduces pipeline disruption
during branching (table 2.3). There are two types of conditional branch instructions: delayed
branch instructions and ordinary branch instructions.
Table 2.3 Delayed Branch Instructions
SH7050 Series CPU
BRA
TRGET
ADD
R1,R0
Description
Executes an ADD before
branching to TRGET
Example of Conventional CPU
ADD.W R1,R0
BRA
TRGET
Multiplication/Accumulation Operation: 16-bit × 16-bit → 32-bit multiplication operations are
executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiplication/accumulation
operations are executed in two to three cycles. 32-bit × 32-bit → 64-bit and 32-bit × 32-bit + 64bit
→ 64-bit multiplication/accumulation operations are executed in two to four cycles.
T Bit: The T bit in the status register changes according to the result of the comparison, and in
turn is the condition (true/false) that determines if the program will branch. The number of
instructions that change the T bit is kept to a minimum to improve the processing speed (table
2.4).
Table 2.4 T Bit
SH7050 Series CPU
CMP/GE R1,R0
BT
TRGET0
BF
TRGET1
ADD
CMP/EQ
BT
#–1,R0
#0,R0
TRGET
Description
T bit is set when R0 ≥ R1. The
program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
T bit is not changed by ADD. T bit
is set when R0 = 0. The program
branches if R0 = 0.
Example of Conventional CPU
CMP.W R1,R0
BGE TRGET0
BLT TRGET1
SUB.W #1,R0
BEQ TRGET
Rev. 5.00 Jan 06, 2006 page 26 of 818
REJ09B0273-0500