SH7050 Datasheet, PDF (340/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Sample Setup Procedure for ATU Channel 0 Input Capture Triggered by Channel 1
Compare-Match: An example of the setup procedure for ATU channel 0 input capture triggered
by channel 1 compare-match is shown in figure 10.47.
1. Set the channel 1 timer I/O control register (TIOR1A) to output compare-match, and set the
timing for compare-match generation in the channel 1 general register (GR1A).
2. Set bits TRG1A and TRG1D to 1 in the trigger selection register (TGSR).
3. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 1 free-
running counter (TCNT1). On compare-match between TCNT1 and GR1A, the compare-
match signal is transmitted to channel 0 as the channel 0 TIA0 and TID0 input capture signal.
Start
Set compare-match ¹
Set TGSR
2
Start counter
3
Signal transmission
Figure 10.47 Sample Setup Procedure for Compare-Match Signal Transmission
Rev. 5.00 Jan 06, 2006 page 320 of 818
REJ09B0273-0500