SH7050 Datasheet, PDF (583/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 18 ROM (128 kB Version)
18.8.3 Error Protection
In error protection, an error is detected when SH7050 runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the SH7050 malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1 and EBR1 settings are retained,
but program mode or erase mode is aborted at the point at which the error occurred. Program
mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit
setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
1. When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
2. Immediately after exception handling (excluding a reset) during programming/erasing
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the bus is released during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 18.9 shows the flash memory state transition diagram.
Rev. 5.00 Jan 06, 2006 page 563 of 818
REJ09B0273-0500