SH7050 Datasheet, PDF (284/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 2—One-Shot Pulse Interrupt Enable (OSE10C): Enables or disables interrupt requests by
OSF10C in TSR when OSF10C is set to 1.
Bit 2:
OSE10C
0
1
Description
OSI10C interrupt requested by OSF10C is disabled
OSI10C interrupt requested by OSF10C is enabled
(Initial value)
Bit 1—One-Shot Pulse Interrupt Enable (OSE10B): Enables or disables interrupt requests by
OSF10B in TSR when OSF10B is set to 1.
Bit 1:
OSE10B
0
1
Description
OSI10B interrupt requested by OSF10B is disabled
OSI10B interrupt requested by OSF10B is enabled
(Initial value)
Bit 0—One-Shot Pulse Interrupt Enable (OSE10A): Enables or disables interrupt requests by
OSF10A in TSR when OSF10A is set to 1.
Bit 0:
OSE10A
0
1
Description
OSI10A interrupt requested by OSF10A is disabled
OSI10A interrupt requested by OSF10A is enabled
(Initial value)
10.2.9 Interval Interrupt Request Register (ITVRR)
The interval interrupt request register (ITVRR) is an 8-bit register. The ATU has one ITVRR
register in channel 0.
Bit: 7
6
5
4
ITVAD3 ITVAD2 ITVAD1 ITVAD0
Initial value: 0
0
0
0
R/W: R/W R/W R/W R/W
3
ITVE3
0
R/W
2
ITVE2
0
R/W
1
ITVE1
0
R/W
0
ITVE0
0
R/W
ITVRR is an 8-bit readable/writable register used for channel 0 interval interrupt bit setting.
ITVRR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Rev. 5.00 Jan 06, 2006 page 264 of 818
REJ09B0273-0500