SH7050 Datasheet, PDF (227/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Block Diagram of Channel 10: Figure 10.8 shows a block diagram of ATU channel 10.
OFF1A–F
OFF2A–B
φ/(m·2ⁿ)
1 ≤ m ≤ 32
0≤n≤5
Clock selection
Comparator
Control logic
OSI10A–H
TOA10
TOB10
TOC10
TOD10
TOE10
TOF10
TOG10
TOH10
Module data bus
Legend:
TCR10: Timer control register 10 (8 bits)
TIERF: Timer interrupt enable register F (8 bits)
TSRF: Timer status register F (8 bits)
DSTR: Down-count start register (8 bits)
TCNR: Timer connection register (8 bits)
DCNT10: Down-counter 10 (16 bits)
Interrupt:
OSI10: One-shot pulse interrupt 10
Inter-channel connection signal:
OFF: Offset compare-match signal
Figure 10.8 Block Diagram of Channel 10
Rev. 5.00 Jan 06, 2006 page 207 of 818
REJ09B0273-0500