SH7050 Datasheet, PDF (322/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
The timing in this case is shown in figure 10.26. In this example, channel 5 is set to PWM mode,
H'00FE is set in GR5A and H'00FF in GR5B, and free-running counter 5 (TCNT5) is started.
When H'0000 (0% duty) is set in GR5A in the interrupt handling routine after a compare-match
with GR5B, a 0% duty waveform cannot be output immediately since the TCNT5 value is already
H'0002, and so 1 continues to be output until the subsequent compare-match with GR5A.
TCNT5 00FA 00FB 00FC 00FD 00FE 00FF 0000 0001 0002
00FE 00FF 0000 0001 0002 0003
TCNT input clock
GR5A
Time from compare-match
to GR5A rewrite
00FF
0000
GR5B
00FF
Compare-match signal
Counter clear signal
Interrupt status flag
GR5A write signal
generated in interrupt
handling routine
PWM output
Period during which
PWM output is 1 although
duty value is 0
Figure 10.26 Channel 5 Waveform when Duty Changes from 100% to 0%
Rev. 5.00 Jan 06, 2006 page 302 of 818
REJ09B0273-0500