SH7050 Datasheet, PDF (216/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
 Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle
output
 Input capture function: Rising-edge, falling-edge, or both-edge detection
 Ten compare-match interrupts/capture interrupts (channel 3/A–D, channel 4/A–D, channel
5/A, B) and three counter overflow interrupts can be generated
• Channels 6 to 9 have four PWM outputs, allowing the following operations:
 Any cycle and duty from 0 to 100% can be set
 Duty buffer register, with transfer to duty register every cycle
 Interrupts can be generated every cycle
• Channel 10 has eight 16-bit down-counters for one-shot pulse output, allowing the following
operations:
 One-shot pulse generation by down-counter
 Down-counter can be rewritten during count
 Interrupt can be generated at end of down-count
 Offset one-shot pulse function available
• High-speed access to internal 16-bit bus
 High-speed access to 16-bit bus for 16-bit registers: timer counters, compare registers, and
capture registers
• 44 interrupt sources
 Four input capture and one overflow interrupt request for channel 0
 Four interval interrupt requests
 Eight dual input capture/compare-match interrupt requests and two counter overflow
interrupt requests for channels 1 and 2
 Ten dual input capture/compare-match interrupt requests and three overflow interrupt
requests for channels 3 to 5
 Four cycle interrupts for channels 6 to 9
 Eight underflow interrupts for channel 10
• Direct memory access controller (DMAC) activation
 The DMAC can be activated by a channel 0 input capture interrupt (ICI0B)
 The DMAC can be activated by a channel 6 cycle register 6 compare-match interrupt
(CMI6)
• A/D converter activation
 The A/D converter can be activated by detection of 1 in bits 10 to 13 of the channel 0 free-
running counter (TCNT0)
Rev. 5.00 Jan 06, 2006 page 196 of 818
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