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SH7050 Datasheet, PDF (682/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/
Section 22 Electrical Characteristics
22.3.3 Bus Timing
Table 22.6 Bus Timing
Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ±10%, AVREF = 4.5 V – AVCC, VSS = AVSS = 0 V,
Ta = –40 to +85°C
Item
Symbol Min
Address delay time
t
—
AD
CS delay time 1
tCSD1
—
CS delay time 2
tCSD2
—
Read strobe delay time 1
tRSD1
—
Read strobe delay time 2
t
—
RSD2
Read data setup time
tRDS
28
Read data hold time
tRDH
0
Write address setup time
tAS
0
Write address hold time
tWR
5
Write strobe delay time 1
t
—
WSD1
Write strobe delay time 2
t
—
WSD2
Write data delay time
tWDD
—
Write data hold time
tWDH
tcyc × m
WAIT setup time
tWTS
15
WAIT hold time
tWTH
0
Read data access time
tACC
tcyc × (n + 2) – 45
Access time from read strobe tOE
tcyc × (n + 1.5) – 45
DACK delay time
tDACKD1
—
Note: n is the number of waits.
m=1: CS assort extended cycle
m=0: Normal cycle (CS assort non-extended cycle)
Max
25
25
25
25
25
—
—
—
—
25
25
35
—
—
—
—
—
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
22.8, 22.9
22.10
22.8, 22.9
Rev. 5.00 Jan 06, 2006 page 662 of 818
REJ09B0273-0500