SH7050 Datasheet, PDF (162/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
9.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)
DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 24-bit read/write registers that
specify the transfer count for the channel (byte count, word count, or longword count). Specifying
a H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216
transfers.
The upper 8 bits of DMATCR always read 0. The write value, also, should always be 0.
The value after power-on resets and in standby mode is undefined.
Always write 0 to the upper 8 bits of a DMATCR.
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Jan 06, 2006 page 142 of 818
REJ09B0273-0500