SH7050 Datasheet, PDF (487/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 15 Compare Match Timer (CMT)
15.4.2 Compare Match Flag Set Timing
The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the
CMCOR register and the CMCNT counter match. The compare match signal is generated upon
the final state of the match (timing at which the CMCNT counter matching count value is
updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare
match signal will not be generated until a CMCNT counter input clock occurs. Figure 15.4 shows
the CMF bit set timing.
CK
CMCNT
input clock
CMCNT
N
0
CMCOR
N
Compare
match signal
CMF
CMI
Figure 15.4 CMF Set Timing
Rev. 5.00 Jan 06, 2006 page 467 of 818
REJ09B0273-0500