SH7050 Datasheet, PDF (261/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 2—Input Capture/Compare-Match Flag (IMF1C): Status flag that indicates GR1C input
capture or compare-match.
Bit 2:
IMF1C
0
1
Description
[Clearing condition]
(Initial value)
When IMF1C is read while set to 1, then 0 is written in IMF1C
[Setting conditions]
• When the TCNT1 value is transferred to GR1C by an input capture signal while
GR1C is functioning as an input capture register
• When TCNT1 = GR1C while GR1C is functioning as an output compare register
Bit 1—Input Capture/Compare-Match Flag (IMF1B): Status flag that indicates GR1B input
capture or compare-match.
Bit 1:
IMF1B
0
1
Description
[Clearing condition]
(Initial value)
When IMF1B is read while set to 1, then 0 is written in IMF1B
[Setting conditions]
• When the TCNT1 value is transferred to GR1B by an input capture signal while
GR1B is functioning as an input capture register
• When TCNT1 = GR1B while GR1B is functioning as an output compare register
Bit 0—Input Capture/Compare-Match Flag (IMF1A): Status flag that indicates GR1A input
capture or compare-match.
Bit 0:
IMF1A
0
1
Description
[Clearing condition]
(Initial value)
When IMF1A is read while set to 1, then 0 is written in IMF1A
[Setting conditions]
• When the TCNT1 value is transferred to GR1A by an input capture signal while
GR1A is functioning as an input capture register
• When TCNT1 = GR1A while GR1A is functioning as an output compare register
Rev. 5.00 Jan 06, 2006 page 241 of 818
REJ09B0273-0500