SH7050 Datasheet, PDF (736/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Timer I/O Control Register 0A
(TIOR0A)
H'FFFF8281 (Channel 0) 8
ATU
Bit:
Bit name:
Initial value:
R/W:
7
IO0D1
0
R/W
6
IO0D0
0
R/W
5
IO0C1
0
R/W
4
IO0C0
0
R/W
3
IO0B1
0
R/W
2
IO0B0
0
R/W
1
IO0A1
0
R/W
0
IO0A0
0
R/W
Bit
Bit Name
Value Description
7, 6
I/O control 0D1, D0 0 0 Input capture disabled
(Initial value)
(IO0D1, IO0D0)
1 Input capture to ICR0D at rising edge
1 0 Input capture to ICR0D at falling edge
1 Input capture to ICR0D at both edges
5, 4
I/O control 0C1, C0 0 0 Input capture disabled
(Initial value)
(IO0C1, IO0C0)
1 Input capture to ICR0C at rising edge
1 0 Input capture to ICR0C at falling edge
1 Input capture to ICR0C at both edges
3, 2
I/O control 0B1, B0
0 0 Input capture disabled
(Initial value)
(IO0B1, IO0B0)
1 Input capture to ICR0B at rising edge
1 0 Input capture to ICR0B at falling edge
1 Input capture to ICR0B at both edges
1, 0
I/O control 0A1, A0
0 0 Input capture disabled
(Initial value)
(IO0A1, IO0A0)
1 Input capture to ICR0A at rising edge
1 0 Input capture to ICR0A at falling edge
1 Input capture to ICR0A at both edges
Rev. 5.00 Jan 06, 2006 page 716 of 818
REJ09B0273-0500