SH7050 Datasheet, PDF (312/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.3.7 Interval Timer Operation
The 8 bits of the interval interrupt request register (ITVRR) are connected to bits 10 to 13 of
TCNT0L in the channel 0 32-bit free-running counter (TCNT0H, TCNT0L). The upper 4 bits
(ITVAD3 to ITVAD0) are used to start A/D converter sampling, and the lower 4 bits (ITVE3 to
ITVE0) generate signals to the interrupt controller (INTC).
For A/D converter activation, an edge sensor is provided for bits 10 to 13 of TCNT0L, and A/D
channel 0 sampling is started when the corresponding bit in TCNT0L changes to 1 as a result of
setting 1 in one of the upper 4 bits (ITVAD3 to ITVAD0) of ITVRR.
For generation of interrupt signals to the INTC, after detection of bits 10 to 13 of TCNT0L by the
edge sensor, when the corresponding bit in TCNT0L changes to 1 as a result of setting 1 in one of
the lower 4 bits (ITVE3 to ITVE0) of ITVRR after detection of bits 10 to 13 of TCNT0L by the
edge sensor, the corresponding flag (IIF0 to IIF3) in timer status register TSRAH is set to 1 and an
interrupt request is sent to INTC. The above four interrupt sources have only one interrupt vector
address, and therefore when more than one of bits ITVE3 to ITVE0 in ITVRR is specified, control
branches to the same vector when any TCNT0 bit corresponding to one of the specified bits
changes to 1.
To suppress interrupts to INTC, or to prevent A/D sampling from being started, all ITVRR bits
should be cleared to 0.
A schematic diagram of the interval timer is shown in figure 10.17.
Rev. 5.00 Jan 06, 2006 page 292 of 818
REJ09B0273-0500